Praveen RTL design, VLSI, systemverilog, verilog,FPGA,ASIC
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Willing to teach all the concepts of RTL design. Will explain everything with example codes. Will explain how to write the scripts to setup the simulation or synthesis environment and optimized ways of RTL coding for better synthesis results.
Will explain CDC techniques, linting, writing test benches or unit tests etc.
I have an experience of 3+ years in RTL design domain and worked on high speed protocols like PCIe, and have experience in Signal processing, RDMA protocol.
I'm willing to explain all the concepts that I know in a simple way possible

Subjects

  • FPGA Design Beginner-Expert

  • SystemVerilog Beginner-Expert

  • ASIC (Application-specific integrated circuit) Beginner-Intermediate

  • Digital design and Verilog HDL Beginner-Expert

Experience

  • Design Engineer 2 (Dec, 2020–Present) at Xilinx, Hyderabad

Education

  • B.Tech (Aug, 2016–Jun, 2020) from National Institute of technology, Patna(NIT PATA)–scored 8.9

Fee details

    ₹600–1,000/hour (US$7.19–11.98/hour)

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