Online Electronics 2 assignment help teacher required in Beylikdüzü
- Beylikdüzü/Istanbul, Turkey
- Posted : Jun 4
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Level : Bachelors/Undergraduate
- Due Date : 05-06-2026
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Requires : Part Time - Posted by : Joe (Student )
- WhatsApp verified +90-**********
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Gender Preference : None
- Available online
- Not available for home tutoring
- Can not travel
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Can communicate in : English
Project: Two-Stage CMOS OPamp Design — Electronics 2, Spring 2026
Design and simulate a two-stage differential-input single-ended output CMOS amplifier in Cadence Virtuoso using the umc65ll process (N_25_LL / P_25_LL transistors).
Specifications to meet:
Supply: 2.5V
DC Gain ≥ 74 dB
Unity Gain Bandwidth ≥ 10 MHz
Overshoot ≤ 5%
Slew Rate ≥ 5 V/μs
Load Capacitance: 100 pF
Total Current ≤ 2000 μA
VOV between 0.15–0.35V for all transistors
What needs to be done:
Full schematic in Cadence (two-stage CMOS opamp with biasing)
Hand calculations for all sizing (gm, ID, W/L, Cc)
5 simulations: DC op point, AC open-loop, transient (1MHz sine), overshoot (100kHz pulse), slew rate (1MHz 1Vpp pulse)
Written report (5 pages max, handwritten calculations)
Deadline: June 5, 2026 11:30 PM — 2 days from now.
