Venkata Sai RTL Design and Verification Engineer
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I am an passionate teacher. I want to make students learn the basics with joy. I always believed that knowledge is the one which can give you confidence. So lets learn with utmost care so that we can be confident. In this process the teacher's role will be crucial. I want to play that crucial role. In my years of experience in teaching i was happy when students ask me more doubts and work on their basics, as it boosts their confidence to crack the interview and also in life.

I would always focus on the all round development of the student. So as a tutor/faculty/guide/friend my duty would be to know the skill level of students, asses him, create him a joy to learn the concept, tell him the drawbacks of the previous method and later revise it frequently with a proper notes. But the student should also contribute the interest to learn which can make the student stand as successful .

Subjects

  • Digital Electronics Beginner-Expert

  • SystemVerilog Beginner-Expert

  • STA (Static Timing Analysis) Beginner-Intermediate

  • Digital design and Verilog HDL Beginner-Expert

  • Uvm (Universal Verification Methodology) Beginner-Expert

Experience

  • RTL Design Lead (Jan, 2021–Present) at Some VLSI Company
    Working on RTL Development of the code and to analyze the Quality Analysis of the Code. Plan for microarchitecture
  • Assistant Professor (Dec, 2015–Dec, 2020) at Reputed College at Chittor, Andhra Pradesh
    Teaching and Research in Digital Electronics, Verilog, System Verilog, UVM, Assertions, STA and CDC

Education

  • M.Tech (Aug, 2013–Jun, 2015) from Top private College in Andhra Pradesh–scored 89%

Fee details

    ₹100–1,500/hour (US$1.05–15.79/hour)

    Teaching fee varies with respect to the student and the personal assistance taken. I want my students to feel comfortable as Knowledge is important and i can even negotiate for the students below poverty level.

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