Tanish Gupta PhD candidate, Biological Sciences
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PhD candidate at IIT Delhi, School for Biological Sciences. Former Analog Engineer and Bachelor of Engineering.
Passionate about academics and teaching. Previously worked as a Teaching Assistant at BITS Pilani Goa. Have provided instruction for tech and biology theory. Am proficient in presentation, compilation, and communication.
Am also a freelance writer, with an English language short story published this year.
Experienced in competitive examinations, to the benefit of syllabus structuring, problem-solving, and concept clearance. Obtained rank 1 in GATE 2025 Biomedical Engineering and JAM 2025 Biotechnology.

The study pattern follows
-breakup of study material
-forming an order for study
-explanation
-doubt clarification
-practice
-revision
Accompanied by notes, assignments, and presentations.
For competitive exams
- a priority would be decided to focus on the most important parts.
- an appropriate study timeline will be set.
- a study routine for daily/weekly tasks will be created for the student.
- problems from many sources would be used.

An interactive approach will be used to ensure that students can engage with the topics firsthand and therefore not depend on specific patterns of questions.
The subject would be approached with basic contextualization followed by the application of concepts from different perspectives to solidify the core concepts. Then the accumulated doubts will be approached to understand the student's standpoint, for which the subject can then be customized.
The goal is to familiarize the student with the topic without forcing them to retain information, while also enhancing the ability to approach problems.

Subjects

  • Biology Grade 10-Grade 12

  • GATE Biotechnology

  • English (CBSE) Grade 10-Grade 12

  • JAM Biotechnology

  • Biology (CBSE) Grade 10-Grade 12

Experience

  • Teaching Assistant (Aug, 2024–Dec, 2024) at BITS PILANI K. K. BIRLA GOA CAMPUS
    Helping students with assignments and doubt clarification.
    Setting assignments and quiz questions.
    Invigilation.
  • Analog Design Engineer (Jun, 2024–Oct, 2024) at Signalchip Innovations, Bangalore
    5G Communication Chip
    Schematic and Layout Design
    Design Debug and Presentation

Education

  • Bachelor of Engineering (Nov, 2020–Jul, 2024) from Birla Institute of Technology and Science Pilani Goa Campus–scored 8.02
  • Higher Secondary (Mar, 2019–Mar, 2020) from Delhi public school jammu–scored 94

Fee details

    ₹100–300/hour (US$1.05–3.16/hour)

    Fees for the first 10 days is 100 for trial allowance.
    Fees thereafter is 300.
    Negotiable.

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