Mr. Marees Kumar Design for Testability
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Professional Summary:
A dedicated and experienced DFT Engineer with a strong background in semiconductor design, testing methodologies, and fault detection techniques. Proficient in implementing DFT strategies to enhance the testability of digital and mixed-signal circuits. Committed to educating and mentoring students and professionals in the principles of DFT, ATPG (Automatic Test Pattern Generation), and related technologies.

Areas of Expertise:
Design for Testability (DFT) methodologies
Test pattern generation and fault simulation
Built-In Self-Test (BIST) techniques
Scan design and boundary scan testing
Fault modeling and coverage analysis
Digital circuit design and verification
Semiconductor manufacturing processes
Industry-standard EDA tools (e.g., Cadence, Synopsys, Mentor Graphics)
Teaching Experience:
Courses Offered:

Introduction to Design for Testability
Advanced DFT Techniques
Digital Circuit Testing and Fault Diagnosis
Practical Applications of ATPG
BIST and Scan Design Methodologies

Subjects

  • Digital Electronics Beginner-Intermediate

  • Chemistry & Biology Beginner-Expert

  • Maths & Reasoning Beginner-Expert

  • Chemistry (12th class)

  • Math (12th)

Experience

No experience mentioned.

Education

  • BE (Jul, 2016–Jul, 2020) from Anna University, Chennai 600025–scored 7

Fee details

    ₹500–1,000/hour (US$5.26–10.53/hour)

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