Chirumalla Venkateswarlu VLSI, CMOS, Physical design and maths
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I am a VLSI Physical Design Engineer with hands-on experience in ASIC design flow from RTL to GDSII. My expertise includes floorplanning, placement, clock tree synthesis, routing, and sign-off checks at advanced technology nodes (16nm/7nm/5nm). I am passionate about delivering timing-closed, congestion-free, and DRC/LVS-clean designs that meet stringent PPA (Power, Performance, Area) requirements.

And I have knowledge on mathematics and CMOS also

I follow an interactive and practical teaching style. Instead of just explaining theory, I connect concepts to real industry use-cases in VLSI Physical Design (RTL–GDSII flow). I encourage students to ask questions freely and solve problems hands-on with EDA tool commands (Innovus/ICC2/PrimeTime).

Blend of industry experience + teaching passion.
Ability to simplify complex topics
Focus on individual student needs—I adapt pace and depth based on background.
Believe in “learn by doing” rather than just listening.
Students gain strong fundamentals + practical exposure to Physical Design.
Have guided learners who successfully cracked interviews at top semiconductor companies.

Helped freshers build industry-ready projects and professionals achieve timing/DRC closure confidence.

Subjects

  • VLSI Intermediate

  • Physical Design Expert

  • VLSI and CMOS Intermediate

  • Mathematical Analysis Intermediate

Experience

  • Trainee engineer (Aug, 2024–Present) at Quest global, Bangalore

Education

  • B.Tech (Jun, 2018–May, 2022) from AMrita Sai Institute of Science and Technology(Paritala,Krishna District)

Fee details

    ₹300–500/hour (US$3.16–5.26/hour)

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