Sudhir Jangra Design and Verification engineer
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I am expert in Verilog, System verilog, C, Cpp, Python,Debugging, Simulation,Emulation, Fpga, STA and other frond end VLSI technologies .Learn from me if you are looking for your career in RTL design or Design verification Roles. I am also working in industry since last 7 years . There is difference in theoretical and practical knowledge. I think you should also have exposure on what kind of work people do in industry and how, Types of RTL design engineers, Soc design engineers, Verification engineers, Static timing analysis engineers. See you !

Subjects

  • C (Programming) Expert

  • Verilog Expert

  • Cpp Expert

  • RTL (Register-transfer level) Expert

  • Design and Verification using SystemVerilog and UVM Expert

Experience

No experience mentioned.

Education

  • B.S (Apr, 2015–Jul, 2019) from SNPS

Fee details

    ₹2,000–5,000/hour (US$21.05–52.63/hour)

Reviews

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