Pratibha VHDL, Verilog, System Verilog, UVM,C, Digital
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Hi Everyone,

I am a Senior Design Verification Engineer with 5 years of hands-on industry experience, working on projects for Samsung, Intel, and AMD.

I specialize in teaching VHDL, Verilog, SystemVerilog, UVM, and core Digital Design concepts in a simple and practical way.

My teaching approach is based on real project experience, so students learn not only the theory but also how these concepts are applied in actual chip design.

I also provide interview preparation in:
• VHDL
• Verilog
• SystemVerilog
• UVM
• C
• Digital Design Concepts

This will help you succeed in interviews and build a strong career in the Semiconductor/VLSI industry.

Note:

If you are seeking any help, please feel free to message your queris

Thanks

Subjects

  • Digital design and Verilog HDL Expert

  • VHDL programming Intermediate

  • Design and Verification using SystemVerilog and UVM Expert

Experience

  • VLSI Faculty (Jul, 2017–Jun, 2020) at 3st Noida

Education

  • M.Tech (Jun, 2014–Jun, 2016) from JSS ACADEMY OF TECHNICAL EDUCATION, NOIDA–scored 7

Fee details

    ₹1,000–3,000/hour (US$10.53–31.58/hour)

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