Santhosh Design Verification, VLSI, UVM, SV, Verilog etc
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Senior Verification Engineer with 8 years of experience specializing in the design and implementation of complex verification environments.
Currently based in Cambridge, UK, leverages a robust skill set honed over an extensive career.
My Expertise was developed during five years in India, mastering cutting-edge verification methodologies, followed by a successful relocation to the UK to tackle advanced verification challenges.
I have a proven track record of ensuring the highest quality of digital designs through meticulous testing and simulation.
Experience bridges two major tech hubs, giving a unique perspective on global engineering standards and best practices.
Iam an expert in advanced verification techniques and a skilled educator who simplifies complex topics.
My teaching approach focuses on practical application, empowering students with the skills needed for real-world engineering challenges. The ability to connect theory with real-world application makes one an effective teacher. This skill is refined through hands-on, practical experience in the industry.
Clear, consistent guidance is provided while fostering a growth mindset, encouraging continuous learning and resilience when facing complex challenges.
My passion lies not only in delivering high-quality, verified designs but also in building the next generation of verification experts.

Subjects

  • Verilog Beginner-Expert

  • UVM (Universal Verification Methodology) Beginner-Expert

  • System verilog Beginner-Expert

  • Design Verification Beginner-Expert


Experience

  • Senior Verificaion engineer (Oct, 2022Present) at Qualcomm Cambridge

Education

  • Btech ECE (May, 2013Jun, 2017) from Raghu institute of technology, vishakapatnam

Fee details

    £530/hour (US$6.7640.54/hour)


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