Yaswanthini RTL design Enginer
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Hello! I’m Yaswanthini, a VLSI design engineer at PrimeSoc Technologies with hands-on experience in Digital and Verilog design.
I teach concepts from basics to project level in a clear and practical way.
I help students understand circuits, FSM, and logic design with real-time examples and interview preparation.

Subjects:Electronics & Communication Engineering | Digital Electronics((Number system, K-map, Flip-Flops, Counters)), Verilog HDL,System Verilog,Pcie, SPI, I2C, AXI|AHB|APB protocols, Aptitude for Engineers ((for freshers preparing for placement)), Cprogramming, Personal & Proffessionaal Developmental skills, Interview TIPS, Business Skills, Tools(Cadence, Model Sim, Quartus Prime),

Subjects

  • Electronics and Communication Engineering Beginner-Expert

Experience

  • RTL Designer (Aug, 2025–Present) at Primesoc Technologies, Bangalore

Education

  • BE Electronics and Communication (Aug, 2019–May, 2023) from Dr Mahalingam college of engineering and technology

Fee details

    ₹500/hour (US$5.26/hour)

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