Praveen Kumar Yadav Python, C, C++, Verilog, System Verilog, UVM
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Skilled in Digital VLSI design with a focus on high-performance, low-complexity hardware architectures for real-time
signal processing. Experienced in developing time-efficient hardware solutions for data-intensive statistical signal pro
cessing applications, specializing in hardware-software co-design for FPGA/ASIC implementations. Proficient in design
ing and verifying RTL modules such as FIFO, RAM, Protocols(UART, PCIe, AMBA AHB2AHB), FFT, Spectrogram,
and PPG Quality Assessment design.

Technical Skills
Programming Languages: Verilog HDL, System Verilog, Python, MATLAB, C, C++, TCL Script.
EDA Tools: Cadence(Incisive, Genus, Innovus), Xilinx(Vivado, HLS, vitis),Synopsys(VCS, ICC), ModelSim
FPGAs: Zybo Z7-10, ZedBoard, PYNQ-Z1
Hardware: Arduino, Raspberry Pi, MSP430F233
Others: Git, GitHub, Technical Writing, Problem Solving, Debugging.

Subjects

  • Python Beginner-Expert

  • Verilog HDL Beginner-Expert

  • C & Data structure Beginner-Expert

  • Design for Testability (DFT) Beginner-Expert

  • Design and Verification using SystemVerilog and UVM Beginner-Expert

Experience

No experience mentioned.

Education

  • MS By Research (Aug, 2023–Jun, 2025) from IIT palakkad kerala–scored 7.56

Fee details

    ₹500–1,000/hour (US$5.26–10.53/hour)

    depends on the syllabus of the subject.

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