Shashi15 Reddy VLSI, RTL coding, Design verification, STA.
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I am a VLSI Design & Verification engineer with strong expertise in SystemVerilog, UVM, RTL design, and industry-standard tools such as Synopsys VCS, Verdi, Cadence, QuestaSim, and ModelSim. I have hands-on experience in writing detailed test plans, developing UVM-based testbenches, running regressions, analyzing functional and code coverage, and debugging complex designs. I have contributed to projects like Rswitch verification, AMBA-APB protocol design and verification, ALU optimization using Wallace Tree multiplier, and Wishbone Memory interface verification. I completed a Design and Verification internship at Semi Design, Noida, and have published papers in neural networks and analog layout optimization. As the founder of the Always@VLSI Club, I have trained 100+ students on Cadence tools and conducted workshops on full-custom, semi-custom, and FPGA design flows. I am proficient in C, Verilog, SystemVerilog, UVM, Python (basic), and Linux, with strong communication skills in English, Telugu, Hindi, and German. My technical expertise, academic contributions, and passion for teaching make me well-suited for a VLSI Design & Verification teaching role. Additionally, I bring a strong commitment to simplifying complex concepts for students and have a proven ability to guide learners through practical, industry-oriented VLSI workflows. I aim to contribute to an institution where I can mentor students, build strong VLSI foundations, and help them prepare for successful semiconductor careers.

Subjects

  • VLSI and CMOS Intermediate-Expert

  • Custom Analog layout design Intermediate-Expert

  • VLSI design Intermediate-Expert

  • VLSI Design and Verification Expert

Experience

No experience mentioned.

Education

  • B. Tech (Jul, 2020–May, 2024) from KL university,vijaywada

Fee details

    ₹500–1,500/hour (US$5.26–15.79/hour)

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