Yaswanth System verilog
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Experienced ASIC Verification Engineer (4+ years) with expertise in functional verification using SystemVerilog and UVM. Proficient in testbench development, coverage planning, scoreboard implementation, assertions, callbacks, and debugging. Worked on Chiplet Technologies (UCle 1.1, BoW), PCle Gen1 PHY, AMBA (AXI, AHB, APB), I2C, and UART. Skilled in analyzing coverage metrics to ensure comprehensive verification.

Hands-on experience with Cadence Xcelium, Synopsys VCS, Verdi, Mentor Questa Sim, and regression tools like VManager and Simsoft. Well-versed in Git, Perforce, DesSync, and JIRA for bug tracking. Implemented functional coverage, assertions, and callbacks to enhance verification quality and efficiency.

Experienced in UVM RAL methodologies, verifying register access and transactions, and ensuring compliance with design specifications. Contributed to top-level verification of PMIC digital blocks, PHY VIP interoperability testing, and VIP development and IP verification and integration. Strong analytical and problem-solving skills, focusing on verification efficiency, optimized test strategies, and high-quality design validation.

Subjects

  • UVM (Universal Verification Methodology) Beginner-Expert

  • Design and Verification using SystemVerilog and UVM Beginner-Intermediate

  • Design Verification Beginner-Intermediate

Experience

  • DV ENGINEER (Aug, 2025–Present) at Qualcomm
  • DV ENGINEER (Jun, 2023–Jul, 2025) at Verifast Technologies
  • DV ENGINEER (Feb, 2022–May, 2023) at Tech Mahindra cerium system Pvt Ltd

Education

  • Electronics and communication engineering (Aug, 2018–May, 2022) from Andhra University, Visakhapatnam, INDIA

Fee details

    ₹5–15/hour (US$0.05–0.16/hour)

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