Akshat Gupta Analog Electronics,CMOS Digital Circuit Design online tutor ₹ 800

I am a dedicated Electronics & Communication Engineering student specializing in Full-Custom Analog IC Design and Physical Verification. With hands-on experience in industry-standard tools like Cadence Virtuoso (Spectre) and LTSpice, I help students and researchers bridge the gap between theoretical circuit equations and practical silicon implementation.My expertise lies in the complete design flow—from schematic entry and small-signal analysis to Layout-aware design, including DRC, LVS, and Parasitic Extraction (PEX). I have a proven track record of designing high-performance circuits at the 90nm node, including a research-level project currently under review for IEEE VDAT 2026.

What I Can Help You With:
a. Cadence Virtuoso Mastery: Schematic design, Testbench setup, and Spectre simulations.
b. Physical Design: Full-custom Layout, solving LVS/DRC errors, and Post-Layout PVT characterization.
c. Analog Building Blocks: Design and analysis of Op-Amps (Miller Compensation), Current Mirrors, Bandgap References, and Differential Amplifiers.
d. Mixed-Signal Systems: Designing SAR ADCs, CDACs, and integrating Verilog-based FSMs with analog circuitry.
e. Assignment & Project Support: Guidance on VLSI lab work, technical report writing, and performance optimization (Gain, Phase Margin, Power, and Area).

Subjects

Analog Electronics Beginner-Intermediate
CMOS Digital Circuit Design Beginner-Expert
Digital design and Verilog HDL Beginner-Intermediate
CMOS Analog Digital VLSI Design Beginner-Intermediate

Experience

No experience mentioned.

Education

B.Tech ECE (Oct, 2023–now) from JSS ACADEMY OF TECHNICAL EDUCATION, NOIDA–scored CGPA : 8.2

Fee details

₹800–2,500/hour (US$8.42–26.31/hour)

Fees vary based on project complexity. Standard tutoring is ₹800/hr. Full-custom IC layout, DRC/LVS debugging, and post-layout parasitic extraction (PEX) for tape-out projects are charged at higher rates.