Janarthanam R S VLSI Frond end Design Engineer
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Hello, I am Jana from Chennai .I am currently working as a VLSI Frond end Design Engineer . I am very much interested in Mathematics and I have very good technical, communication and problem solving skills . I have a strong knowledge on Hardware description language such as Verilog and System Verilog. I use vim or gvim text editor and I have got experience on some professional tools for Simulation(Synopsys-VCS,Cadence-Simvision,Mentor-Questasim), Synthesis(Synopsys-Design Vision),LEC(Synopsys-Formality),Lint(Synopsys-Spyglass,Cadence-Jaspergold)and CDC(Synopsys-Spyglass) . I am familiar in working with LINUX and UNIX terminals for ASIC design and I have done many projects in 5nm & 7nm technology .I have the ability to share my knowledge with proper methods. I will ensure that I can help you to understand all the topics which I am going to cover and also assure you that I wont waste your valuable time.

Subjects

  • Digital Electronics Beginner-Expert

  • Verilog Beginner-Expert

  • Digital circuits Beginner-Expert

  • Synopsys VCS Beginner-Expert

  • Synopsys Design Compiler Beginner-Intermediate

  • Digital IC design Beginner-Expert

  • Digital Circuit Design Beginner-Expert

  • System Design (Analog/Digital) Beginner-Intermediate

  • Digital design Beginner-Expert

Experience

No experience mentioned.

Education

  • Electronics and Communication Engineering (Aug, 2013–May, 2017) from Anna University

Fee details

    ₹500–1,000/hour (US$5.99–11.98/hour)

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