Arvind Dandotiya Fpga,VHDL,xilinx,vivado,lattice,altera
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I have more than 5 year of industrial experience in FPGA Domain that is very helpful for students those who wants to choose frontend vlsi engineer.
I have hands on experience with fpga tools and languages like vhdl and verilog. Why i am saying here vhdl language why because vhdl language is the key language for fpga design and verification engineer.
I can also teach digital design concept that is very help full for fpga design and verification engineer.
In tool i have hands on experience with xilinx, microsemi,lattice diamond, and intel.

Subjects

  • FPGA Design Intermediate-Expert

  • Xilinx Vivado Intermediate-Expert

  • VHDL/Verilog Intermediate-Expert

Experience

No experience mentioned.

Education

  • Esdm (Mar, 2016–Oct, 2016) from CDAC Hyderabad
  • BR (Jun, 2009–Jun, 2013) from Jijel University

Fee details

    ₹500–5,000/hour (US$5.99–59.91/hour)

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