Chethan Kumar Digital designer

I have 8+ years of experience in digital/FPGA/ASIC design and verification, I have guided a significant number of students on their university projects. Most of the projects were FPGA based.
Since I have been working in the semiconductor industry for quite a long time and have written a significant number of blogs on various topics, I believe I can deliver the best when it comes to teaching, with great real-time examples and tutorials.
I always believe in learning with live example and i apply the same while teaching.
I have a habit of creating an online one notes for anything I learn so that it can be easily referred to when it is required. I advise the same method to anyone I am tutoring.

Subjects

  • Maths (Beginner-Expert)

  • C (Beginner-Intermediate)

  • Algebra (Beginner-Expert)

  • Digital Electronics (Beginner-Expert)

  • VHDL (Beginner-Intermediate)

  • FPGA (Beginner-Expert)

  • Embedded software (Beginner-Intermediate)

  • Digital circuits (Beginner-Expert)

  • Xilinx Vivado (Beginner-Intermediate)

  • Basic Electronics (Beginner-Intermediate)

  • Digital Designing (Beginner-Expert)

  • SystemVerilog (Beginner-Expert)

  • Uvm (Beginner-Intermediate)

  • Spoken Kannada (Beginner-Expert)

  • ASIC (Beginner-Intermediate)

  • 8051 Microcontroller (Beginner-Expert)

  • Verilog HDL (Beginner-Expert)


Experience

  • Digital Designer (Oct, 2018 - Present) at ST microelectronics, SIngapore
    •Working on SOC integration, RTL design, synthesis and verification, .
  • Hewlett Packard Enterprise, Singapore (Jun, 2016 - Oct, 2018) at FPGA RTL Design Engineer- R&D Aruba Networking
    •Worked on FPGA logic development: architecture, implementation, functional simulation, and verification.
    • Formal verification.
    •Integration of custom logic, generated IP cores and hard IP blocks to meet system requirements.
    • Microarchitecture and Developing Reusable IPs
    •Define test cases and full pledged system level test bench development using system verilog constructors.
    •CPLD design.
    •TTL and Python scripting for Testing FPGA modules on hardware
  • Graduate Research Assistant (part time), Centre for High Performance Embedded Systems (CHiPES) (Oct, 2015 - Apr, 2016) at Nanyang Technological University, Singapore
    • RTL Development and testing of deflection torus multi-layer NOC (Network on hip).
    • Test plan and test bench development to test MIPS overlay and multi-layer NOC
    • Added new set of customized instructions (SEND/RECEIVE) to the mipsfpga soft processor to support direct data transfer between the processors
    • Building 256-core microAptive MIPS overlay for FPGA’s using MIPSfpga soft processor and establish communication among the processors through NOC.
    • Automation of Xilinx floor plan (creating location constraints) process to place NOC routers on Virtex6 FPGA in a folded structure to achieve higher performance.
    • Implementation of Real Time Audio Spectrum display on ZedBoard
    • Shell scripting for collecting results and R scripting for analyzing the results and plotting.
  • FPGA Design Engineer (Jun, 2011 - May, 2014) at Mistral Solutions Pvt. Ltd, Bangalore
    • Involved in creating PLD (Programmable Logic Design) document for various projects.
    • Testing and Debugging of FPGA modules on hardware.
    • Test plan and test bench development for various projects.
    • Design and implementation of I2C, GPMC, UART and SPI slave, DDR3 and PCI user interface, Video resolution detector and Video test pattern generator.
    • Worked on FPGA implementation flow, Functional and Timing simulation.
    • Worked on video interfaces like Triple rate SDI, YCBCR and HDMI.

Education

  • Masters (Jul, 2015 - Aug, 2016) from Nanyang Technological University

Fee details

    SG$15-25/hour (US$10.87-18.12/hour)


8 Reviews
4.9 out of 5

User Photo May 14, 2020
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Professional

He’s so professional and he can solve even complex circuits ?? I highly recommend him


User Photo May 7, 2020
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Programmable Devices

He is very good and Super in Programmable Devices


User Photo April 21, 2020
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Amazing, actually knows what he is talking about

He could explain everything and did not trick me, actually knew what he was talking about.


User Photo April 21, 2020
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Verilog HDL

I think you are an awesome professor. You have been so clear when it came to understanding Verilog and its basics. Thank you so much for such a wonderful and enriching help. You made it very constructive to learn and I'd definitely ask for more help in the future. All details required were submitted in a timely manner and my understanding was the main priority.


User Photo April 6, 2020
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Very experienced Verilog tutor

Amazing tutor ! Very good at verilog and digital logic.


User Photo March 31, 2020
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Great Verilog Tutor

the result was good.


User Photo March 29, 2020
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Great Verilog Tutor

Helped me quickly see the mistake in one of my University Assignments by supplying a helpful diagram.


User Photo March 29, 2020
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Great!

The result was great!