Chethan Kumar Digital designer

Since i have been working in a semiconductor industry for quite a long time and have written significant number of blogs on various topics, believe i can deliver the best when it comes to teaching, with great real time examples and tutorials.
I always believe in learning with live example and i apply the same while teaching.
I have an habit of crating a online one notes for anything i learn, so that it can be easily referred when it is required. I advice the same method to anyone i am tutoring.


  • Maths (Beginner-Expert)

  • SystemVerilog (Beginner-Expert)

  • FPGA (Beginner-Expert)

  • Digital Designing (Beginner-Expert)

  • C (Beginner-Intermediate)

  • 8051 Microcontroller (Beginner-Expert)

  • Algebra (Beginner-Expert)

  • Digital circuits (Beginner-Expert)

  • Basic Electronics (Beginner-Intermediate)

  • ASIC (Beginner-Intermediate)

  • Digital Electronics (Beginner-Expert)

  • Embedded software (Beginner-Intermediate)

  • Xilinx Vivado (Beginner-Intermediate)

  • Verilog HDL (Beginner-Expert)

  • VHDL (Beginner-Intermediate)

  • Uvm (Beginner-Intermediate)

  • Spoken Kannada (Beginner-Expert)


  • Digital Designer (Oct, 2018 - Present) at ST microelectronics, SIngapore
    •Working on SOC integration, RTL design, synthesis and verification, .
  • Hewlett Packard Enterprise, Singapore (Jun, 2016 - Oct, 2018) at FPGA RTL Design Engineer- R&D Aruba Networking
    •Worked on FPGA logic development: architecture, implementation, functional simulation, and verification.
    • Formal verification.
    •Integration of custom logic, generated IP cores and hard IP blocks to meet system requirements.
    • Microarchitecture and Developing Reusable IPs
    •Define test cases and full pledged system level test bench development using system verilog constructors.
    •CPLD design.
    •TTL and Python scripting for Testing FPGA modules on hardware
  • Graduate Research Assistant (part time), Centre for High Performance Embedded Systems (CHiPES) (Oct, 2015 - Apr, 2016) at Nanyang Technological University, Singapore
    • RTL Development and testing of deflection torus multi-layer NOC (Network on hip).
    • Test plan and test bench development to test MIPS overlay and multi-layer NOC
    • Added new set of customized instructions (SEND/RECEIVE) to the mipsfpga soft processor to support direct data transfer between the processors
    • Building 256-core microAptive MIPS overlay for FPGA’s using MIPSfpga soft processor and establish communication among the processors through NOC.
    • Automation of Xilinx floor plan (creating location constraints) process to place NOC routers on Virtex6 FPGA in a folded structure to achieve higher performance.
    • Implementation of Real Time Audio Spectrum display on ZedBoard
    • Shell scripting for collecting results and R scripting for analyzing the results and plotting.
  • FPGA Design Engineer (Jun, 2011 - May, 2014) at Mistral Solutions Pvt. Ltd, Bangalore
    • Involved in creating PLD (Programmable Logic Design) document for various projects.
    • Testing and Debugging of FPGA modules on hardware.
    • Test plan and test bench development for various projects.
    • Design and implementation of I2C, GPMC, UART and SPI slave, DDR3 and PCI user interface, Video resolution detector and Video test pattern generator.
    • Worked on FPGA implementation flow, Functional and Timing simulation.
    • Worked on video interfaces like Triple rate SDI, YCBCR and HDMI.


  • Masters (Jul, 2015 - Aug, 2016) from Nanyang Technological University

Fee details

    SG$8-15/hour (US$5.93-11.11/hour)


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