ashish khachane Rtl design

I am RTL Design Engineer with 6.7 years experience.I can help you in VLSI, Electrical,Electronics Communication Assignments Projects.I am best in VHDL,
Verilog,System Verilog. I worked on XILINX, QUARTUS, MODELSIM, QUESTSIM, ISE, TCL, VIVADO. I will give you whole details of your assignment / project along with code.I will give you 100% unique work.My all work is plagiarism free.In case of projects, I will apply charges as per projects requirement.I assure you that I will provide you genuine work within your deadline as per your requirement.I have good experience in doing this type of assignment projects and writing work.I am BE,MTECH qualified person with good percentiles.

Subjects

  • VHDL (Expert)

  • Verilog (Expert)

  • Xilinx Vivado (Expert)

  • C (Expert)

  • Matlab (Expert)


Experience

  • RTL Design Engineer (May, 2016 - Jan, 2019) at jdmtech semiconductor
    RTL Design Engineer

Education

  • MTech (Jun, 2012 - Jun, 2014) from Rtmnu Nagpur India
  • BE (Jun, 2008 - May, 2012) from SGBAU Amravati, Maharashtra

Fee details

    US$10-30/hour (US$10.0-30.0/hour)

    10$ per hour